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MC14018B Presettable Divide-By-N Counter
The MC14018B contains five Johnson counter stages which are asynchronously presettable and resettable. The counters are synchronous, and increment on the positive going edge of the clock. Presetting is accomplished by a logic 1 on the preset enable input. Data on the Jam inputs will then be transferred to their respective Q outputs (inverted). A logic 1 on the reset input will cause all Q outputs to go to a logic 1 state. Division by any number from 2 to 10 can be accomplished by connecting appropriate Q outputs to the data input, as shown in the Function Selection table. Anti-lock gating is included in the MC14018B to assure proper counting sequence.
Features http://onsemi.com MARKING DIAGRAMS
PDIP-16 P SUFFIX CASE 648
16 MC14018BCP AWLYYWWG 1
* Fully Static Operation * Schmitt Trigger on Clock Input * Capable of Driving Two Low-Power TTL Loads or One Low-Power * *
Schottky TTL Load Over the Rated Temperature Range Pin-for-Pin Replacement for CD4018B Pb-Free Packages are Available*
16 SOIC-16 D SUFFIX CASE 751B 1 14018BG AWLYWW
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V V mA mW C C C
A WL, L YY, Y WW, W G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
August, 2005 - Rev. 6
Publication Order Number: MC14018B/D
MC14018B
PIN ASSIGNMENT
Din JAM 1 JAM 2 Q2 Q1 Q3 JAM 3 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD R C Q5 JAM 5 Q4 PE JAM 4
FUNCTIONAL TRUTH TABLE
Clock Reset 0 0 0 0 1 Preset Enable 0 0 1 1 X Jam Input X X 0 1 X Qn Qn Dn* 1 0 1
X X X
*Dn is the Data input for that stage. Stage 1 has Data brought out to Pin 1.
ORDERING INFORMATION
Device MC14018BCP MC14018BCPG MC14018BD MC14018BDG MC14018BDR2 MC14018BDR2G Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) Shipping 500 Units / Rail 500 Units / Rail 48 Units / Rail 48 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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II I II II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIII IIII I I I I IIII I II I I I I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I I I I I I I I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I I IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII III I II II IIII I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII III I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I I I I III II IIII III I II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIII II IIII I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I I III II IIII I II II IIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII IIIII I I II II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Quiescent Current (Per Package) Input Capacitance (Vin = 0) Input Current Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) Output Voltage Vin = VDD or 0 (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) "1" Level (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Vin = 0 or VDD Characteristic "1" Level "0" Level Source Sink Symbol VOH VOL IOH VIH IDD IOL Cin VIL Iin IT VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 -- - 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- --
2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001.
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MC14018B
- 55_C
3 0.1 0.05 0.05 0.05 Max 5.0 10 20 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 0.51 1.3 3.4 Min 3.5 7.0 11 IT = (0.3 mA/kHz) f + IDD IT = (0.7 mA/kHz) f + IDD IT = (1.0 mA/kHz) f + IDD -- -- -- -- -- -- -- -- -- -- -- 0.00001 Typ (Note 2) - 4.2 - 0.88 - 2.25 - 8.8 0.005 0.010 0.015 25_C 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 5.0 5.0 10 15 0 0 0 0.1 0.05 0.05 0.05 Max 5.0 10 20 7.5 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- 125_C 1.0 0.05 0.05 0.05 Max 150 300 600 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- mAdc mAdc mAdc mAdc mAdc Unit Vdc Vdc Vdc Vdc pF
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I III IIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I III III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I IIIII I II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I I IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIII I IIII IIII I II I I I I I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII
5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Clock Pulse Frequency
Clock Rise and Fall Time
Reset or Preset Enable Pulse Width
Clock Pulse Width
Data (Jam Inputs)-to-Preset Enable Hold Time
Setup Time Data (Pin 1) to Clock
Preset Enable to Q tPLH, tPHL = (0.90 ns/pF) CL + 325 ns tPLH, tPHL = (0.36 ns/pF) CL + 132 ns tPLH, tPHL = (0.26 ns/pF) CL + 81 ns
Reset to Q tPLH = (0.90 ns/pF) CL + 325 ns tPLH = (0.36 ns/pF) CL + 132 ns tPLH = (0.26 ns/pF) CL + 81 ns
Propagation Delay Time Clock to Q tPLH, tPHL = (0.90 ns/pF) CL + 265 ns tPLH, tPHL = (0.36 ns/pF) CL + 102 ns tPLH, tPHL = (0.26 ns/pF) CL + 72 ns
Output Rise and Fall Time tTLH, tTHL = (1.35 ns/pF) CL + 32 ns tTLH, tTHL = (0.6 ns/pF) CL + 20 ns tTLH, tTHL = (0.4 ns/pF) CL + 20 ns
Jam Inputs to Preset Enable
Characteristic
ANY OUTPUT
ANY INPUT
Figure 1. Switching Time Waveforms
20 ns
tPLH
tTLH
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90% 50% 10% 50% 10% tTLH, tTHL tTLH, tTHL Symbol
MC14018B
tPLH, tPHL
tWH
tWH
tsu
fcl
th
90%
4 tTHL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 20 ns tPHL VOL VOH VSS VDD Min 290 130 110 400 200 160 540 500 480 200 100 80 200 100 80 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All Types No Limit Typ (Note 6) 145 65 55 200 100 80 270 250 240 370 150 100 370 150 100 310 120 85 100 50 40 0 0 0 0 0 0 2.5 6.5 8.0 1.25 3.25 4.0 Max 740 300 200 740 300 200 620 240 170 200 100 80 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MHz Unit ns ns ns ns ns ns ns ns ns ns
MC14018B
CLOCK RESET PRESET ENABLE JAM 1 JAM 2 1 0 1 0 1 0 1 0 1 0 DON'T CARE UNTIL PRESET ENABLE GOES HIGH 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
TIMING DIAGRAM (Q5 Connected to Data Input)
JAM 3 JAM 4 JAM 5 Q1 Q2 Q3 Q4 Q5
FUNCTION SELECTION
Counter Mode Divide by 10 Divide by 8 Divide by 6 Divide by 4 Divide by 2 Divide by 9 Divide by 7 Divide by 5 Divide by 3 Connect Data Input (Pin 1) to: Q5 Q4 Q3 Q2 Q1 Q5 * Q4 Q4 * Q3 Q3 * Q2 Q2 * Q1
Comments
No external components needed.
LOGIC DIAGRAM
Gate package needed to provide AND function. Counter Skips all 1's state JAM 1 2 JAM 2 3 JAM 3 7 JAM 4 9 JAM 5 12
CLOCK 14 DATA 1
CLOCK SHAPER D C RP S Q D C S Q D C RP S Q D C RP S Q D C RP S Q
Q RP
RESET
15
PRESET ENABLE
10 VDD = PIN 16 VSS = PIN 8
5 Q1
4 Q2
6 Q3
11 Q4
13 Q5
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MC14018B
PACKAGE DIMENSIONS
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE T
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
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MC14018B
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
16 9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC14018B
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MC14018B/D

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